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proposal.bib 0 → 100755
View file @ 37bcac61
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@article{Riefert2016b,
abstract = {Software-based self-Test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-The-Art manual approaches.},
author = {Riefert, Andreas and Cantoro, Riccardo and Sauer, Matthias and {Sonza Reorda}, Matteo and Becker, Bernd},
doi = {10.1109/TVLSI.2016.2538800},
file = {:home/phil/.docs/Riefert et al. - 2016 - A Flexible Framework for the Automatic Generation of SBST Programs(2).pdf:pdf},
issn = {10638210},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
keywords = {Automatic software-based self-Test (SBST),SBST,SBST for in-field test,functional ATPG,microprocessor test},
number = {10},
pages = {3055--3066},
publisher = {IEEE},
title = {{A Flexible Framework for the Automatic Generation of SBST Programs}},
volume = {24},
year = {2016}
}
@article{Servadei2019,
abstract = {Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to allow plenty of options how to eventually realize a system. This allows for design exploration which in turn heavily relies on knowing the costs of different design configurations (with respect to hardware usage as well as firmware metrics). To this end, methods for cost estimation are frequently applied in industrial practice. However, currently used methods for cost estimation oversimplify the problem and ignore important features - leading to estimates which are far off from the real values. In this work, we address this problem for memory systems. To this end, we borrow and re-adapt solutions based on Machine Learning (ML) which have been found suitable for problems from the domain of Computer Vision (CV) - in particular age determination of persons depicted in images. We show that, for an ML approach, age determination from the CV domain is actually very similar to cost estimation of a memory system.},
author = {Servadei, Lorenzo and Zennaro, Elena and Devarajegowda, Keerthikumara and Manzinger, Martin and Ecker, Wolfgang and Wille, Robert},
doi = {10.23919/DATE.2019.8714961},
file = {:home/phil/.docs/Servadei et al. - 2019 - Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision.pdf:pdf},
isbn = {9783981926323},
journal = {Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019},
pages = {1277--1280},
publisher = {EDAA},
title = {{Accurate Cost Estimation of Memory Systems Inspired by Machine Learning for Computer Vision}},
year = {2019}
}
@article{Ecker2019,
abstract = {This paper presents an automated process for end-to-end embedded system design following OMG's model driven architecture (MDA) vision. It tackles a major challenge in automation: bridging the large semantic gap between the specification and the target code. The shown MDA adaption proposes an uniform and systematic way by splitting the translation process into multiple layers and introducing design platform independent and implementation independent views.In our adaption of MDA, we start with a formalized specification and we end with code (view) generation. The code is then compiled (software) or synthesized (hardware) and finally assembled to the embedded system design. We split the translation process in Model-of-Thing (MoT), Model-of-Design (MoD) and Model-of-View (MoV) layers. MoTs represent the formalized specification, MoDs contain the implementation architecture in a view independent way, and MoVs are implementation dependent and view dependent, i.e., specific details in target language.MoT is translated to MoD, MoD is translated to MoV and MoV is finally used to generate views. The translation between the Models is based on templates, that reflect design and coding blueprints. The final step of the view generation is itself part of generation. The Model MoV and the unparse method are generated from a view language description.The approach has been successfully adapted for generating digital hardware (RTL), properties for verification (SVA), and snippets of firmware that have been successfully synthesized to an FPGA.},
author = {Ecker, Wolfgang and Devarajegowda, Keerthikumara and Werner, Michael and Han, Zhao and Servadei, Lorenzo},
doi = {10.23919/DATE.2019.8715154},
file = {:home/phil/.docs/Ecker et al. - 2019 - Embedded Systems' Automation following OMG's Model Driven Architecture Vision.pdf:pdf},
isbn = {9783981926323},
journal = {Proceedings of the 2019 Design, Automation and Test in Europe Conference and Exhibition, DATE 2019},
keywords = {Code Generation,Design Automation,Metamodeling,Model Driven Architectrue,Model based Design},
pages = {1301--1306},
publisher = {EDAA},
title = {{Embedded Systems' Automation following OMG's Model Driven Architecture Vision}},
year = {2019}
}
@article{Oyeniran2020,
author = {Oyeniran, Adeboye Stephen and Ubar, Raimund and Jenihhin, Maksim and Raik, Jaan},
doi = {10.1007/s10836-020-05856-7},
file = {:home/phil/.docs/Oyeniran et al. - 2020 - High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors.pdf:pdf},
isbn = {1083602005856},
issn = {0923-8174},
journal = {Journal of Electronic Testing},
keywords = {Processor testing,High-level control fault model,F,fault simulation,functional test generation,high-level control fault model,high-level fault coverage,low-level fault redundancy,processor testing},
pages = {87--103},
publisher = {Journal of Electronic Testing},
title = {{High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors}},
year = {2020}
}
@article{pulpino,
title = {{Pulpino CPU}}
}
@article{Riefert2016a,
abstract = {Software-based self-Test (SBST) techniques are used to test processors and processor cores against permanent faults introduced by the manufacturing process or to perform in-field test in safety-critical applications. However, the generation of an SBST program is usually associated with high costs as it requires significant manual effort of a skilled engineer with in-depth knowledge about the processor under test. In this paper, we propose an approach for the automatic generation of SBST programs. First, we detail an automatic test pattern generation (ATPG) framework for the generation of functional test sequences. Second, we describe the extension of this framework with the concept of a validity checker module (VCM), which allows the specification of constraints with regard to the generated sequences. Third, we use the VCM to express typical constraints that exist when SBST is adopted for in-field test. In our experimental results, we evaluate the proposed approach with a microprocessor without interlocked pipeline stages (MIPS)-like microprocessor. The results show that the proposed method is the first approach able to automatically generate SBST programs for both end-of-manufacturing and in-field test whose fault efficiency is superior to those produced by state-of-The-Art manual approaches.},
author = {Riefert, Andreas and Cantoro, Riccardo and Sauer, Matthias and {Sonza Reorda}, Matteo and Becker, Bernd},
doi = {10.1109/TVLSI.2016.2538800},
file = {:home/phil/.docs/Riefert et al. - 2016 - A Flexible Framework for the Automatic Generation of SBST Programs.pdf:pdf},
issn = {10638210},
journal = {IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
keywords = {Automatic software-based self-Test (SBST),SBST,SBST for in-field test,functional ATPG,microprocessor test},
number = {10},
pages = {3055--3066},
publisher = {IEEE},
title = {{A Flexible Framework for the Automatic Generation of SBST Programs}},
volume = {24},
year = {2016}
}
@article{riscvspec,
title = {{Risc-V Specifications}},
url = {https://riscv.org/specifications/}
}
@article{Balcarek2013,
abstract = {Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefit from an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS'85, '89 and ITC'99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SAT-based tools for CTPG are given. {\textcopyright} 2012 Elsevier B.V. All rights reserved.},
author = {Balcarek, Jiri and Fiser, Petr and Schmidt, Jan},
doi = {10.1016/j.micpro.2012.09.010},
file = {:home/phil/.docs/Balcarek, Fiser, Schmidt - 2013 - Techniques for SAT-based constrained test pattern generation.pdf:pdf},
issn = {01419331},
journal = {Microprocessors and Microsystems},
keywords = {ATPG,Constrained test,Implicit representation,SAT,Testing},
number = {2},
pages = {185--195},
title = {{Techniques for SAT-based constrained test pattern generation}},
volume = {37},
year = {2013}
}
@article{riscv,
title = {{Risc-V}},
url = {https://www.riscv.org}
}
@article{Psarakis2010,
author = {Psarakis, Mihalis and Gizopoulos, Dimitris and Sanchez, Ernesto and Reorda, Matteo Sonza and Torino, Politecnico},
file = {:home/phil/.docs/Psarakis et al. - 2010 - Microprocessor Software- Based Self-Testing.pdf:pdf},
pages = {4--19},
title = {{Microprocessor Software- Based Self-Testing}},
year = {2010}
}
@article{Riefert2016,
abstract = {Functional test and software-based self-test (SBST) approaches for processors are becoming popular as they enable low-cost production tests and are often the only solution for in-field tests. With the increasing use of volume diagnosis, efficient and cost-effective diagnosis methods are required. A high quality functional or SBST test program can be used to perform logic fault diagnosis with low-cost test equipment and therefore significantly reduce the cost of diagnosis. We present a framework for the automatic generation of functional diagnostic sequences for stuck-at faults. The framework allows a user to specify constraints imposed by the employed test environment and generates diagnostic sequences satisfying these constraints. Furthermore, the framework is able to prove the equivalence of faults under the specified constraints. This enables to compute the best possible diagnostic quality that can be reached under the given environmental constraints. Also, it gives the necessary information for implementing selective DFT techniques in order to differentiate faults which cannot be distinguished otherwise. In our experiments we evaluated a MIPS-like processor. The results show that our approach can effectively distinguish fault pairs or prove their equivalence, under different environmental constraints. To the best, of our knowledge, this is the first approach which, enables the automatic generation of diagnostic SBST, programs and allows to eectively prove the equivalence of faults in functional and SBST test environments.},
author = {Riefert, Andreas and Cantoro, Riccardo and Sauer, Matthias and Reorda, Matteo Sonza and Becker, Bernd},
doi = {10.1109/VTS.2016.7477279},
file = {:home/phil/.docs/Riefert et al. - 2016 - Effective generation and evaluation of diagnostic SBST programs.pdf:pdf},
isbn = {9781467384544},
journal = {Proceedings of the IEEE VLSI Test Symposium},
pages = {1--6},
publisher = {IEEE},
title = {{Effective generation and evaluation of diagnostic SBST programs}},
volume = {2016-May},
year = {2016}
}
@article{Grillner2009,
abstract = {The spinal cord contains a great number of interneurons that form networks that can be called into action from the brain and that play a critical role in shaping our motor behavior. These circuits coordinate our muscles as we walk and fine-tune different types of protective and autonomic reflexes. In this brief account, we summarize what we know about the integrative properties of these spinal circuits. {\textcopyright} 2009 Elsevier Ltd All rights reserved.},
author = {Grillner, S.},
doi = {10.1016/B978-008045046-9.01341-3},
file = {:home/phil/.docs/Grillner - 2009 - SAT-Based ATPG - Pattern Generation.pdf:pdf},
isbn = {9780080450469},
journal = {Encyclopedia of Neuroscience},
keywords = {Lamprey,Locomotor network,Modeling,Robot,Spinal cord,Steering},
pages = {487--494},
title = {{SAT-Based ATPG - Pattern Generation}},
year = {2009}
}
@article{Sensitization2016,
author = {Sauer, Matthias and Becker, Bernd and Polian, Ilia and Member, Senior},
file = {:home/phil/.docs/Sauer et al. - 2016 - PHAETON A SAT-Based Framework for Timing-aware Path Sensitization.pdf:pdf},
number = {6},
pages = {1869--1881},
publisher = {IEEE},
title = {{PHAETON : A SAT-Based Framework for Timing-aware Path Sensitization}},
volume = {65},
year = {2016}
}
proposal.md 0 → 100644
View file @ 37bcac61
---
title: 'Master/Bachelor - Thesis/Project: The Greatest Work Humanity Has Ever Lazyed Eyes Upon'
bibliography: proposal.bib
author: |
| your name
| <youremail@tf.uni-freiburg.de>
...
EDIT THE proposal.bib FOR YOUR REFERENCES (or you use a bibliography manager)
Scale4Edge hat ein Ökosystem für eine skalierbare und flexibel erweiterbare Edge-Computing-Plattform, welches auf der freien RISC-V-Instruktionssatzarchitektur basiert, zum Ziel. Die RISC-V-Plattform ist durch den generischen Aufbau der Standard-ISA[@riscvspec] skalierbar, die ergänzend zu einem 32-Bit-Basis-Instruktionssatz, eine Vielzahl von optionalen Instruktionen, z.B. zur Unterstützung von nicht unterbrechbaren Instruktionen, definiert. Das umfasst die unterschiedlichen Komponenten zur Ausführung der in der ISA definierten unterschiedlichen Instruktionen sowie vereinfachte Ausprägungen der Exception-Behandlung, adressiert unterschiedliche Pipeline-Architekturen, Multi-Core-Architekturen, Co-Prozessoren und beinhaltet Hardware-Unterstützung wie z.B. für Interrupts und Timer/Counter. Hinsichtlich der Skalierbarkeit der Hardware stehen Ergänzungen für nichtfunktionale Eigenschaften wie Energieeffizienz, Fehlertoleranz, Robustheit und Sicherheit (Safety und Security) im Fokus. Verschiedene Maßnahmen wie das Härten von Registern durch Fehlerkorrekturbits, die Skalierung der Taktfrequenz oder der Schutz von Speicherbereichen durch eine MPU sind Beispiele hierfür. Verschiedene Verifikations-, Analyse- und Debug-Möglichkeiten adressieren dies.
Wir konzentrieren uns auf Methoden und Werkzeuge, die einen effizienten Selbsttest der Mikroarchitektur ermöglichen. Dieser Selbsttest soll die Korrektheit der vorliegenden Hardware sowohl unmittelbar nach der Herstellung als auch im Betrieb gewährleisten. Ziel ist ein möglichst weitgehender software-basierter Selbsttest (SBST), der automatisiert generiert wird und bei Bedarf mit dem (Selbst-)Test einzelner Komponenten kombiniert werden kann. Die Zugänglichkeit dieser Komponenten und die Integration zu einem Gesamttest erfolgt mittels nicht-funktionaler Chip-Infrastruktur und einen kontrollierten Zugriff auf Testschnittstellen ermöglicht.
Das Ziel dieser Masterarbeit ist ein systematisches Review verwandter Arbeiten in den Bereichen von Automatic Test Pattern Generation (ATPG), und Software-Based-Self-Test (SBST) für Prozessoren. Dazu sollen aktuelle wissenschaftliche Arbeiten zusammengefasst, klassifiziert und ein Überblick über den mometanen Stand der Forschung geschaffen werden [@Balcarek2013; @Sensitization2016; @Riefert2016; @Riefert2016a; @Psarakis2010].